1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having input circuits for receiving input signals.
2. Description of the Related Art
Recently, semiconductor integrated circuits are ever decreasing in power supply voltage (operation voltage) for the sake of finer transistor structures, reduced power consumption, and so on. The threshold voltages of the transistors hardly depend on the power supply voltage. With the decreasing power supply voltage, the threshold voltages of the transistors thus increase in relation to the power supply voltage. As a result, circuits made of transistors tend to decrease in operation margin.
FIG. 1 shows an example of an input circuit for receiving an input signal supplied from exterior.
The input circuit has a latching part 1, a precharging part 2, a feedback part 3, an input part 4, a power supply connection part 5, and a buffer part 6. The latching part 1 is composed of two CMOS inverters 1a and 1b having inputs and outputs connected to each other. The precharging part 2 is composed of two pMOS transistors 2a and 2b which are connected at their drains to the input nodes ND1 and ND2 of the CMOS inverters 1a and 1b, respectively. The pMOS transistors 2a and 2b are connected to a power supply line VDD at their sources, and receive a clock signal CLK at their gates.
The feedback part 3 is composed of two nMOS transistors 3a and 3b which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters 1a and 1b. The gates of the nMOS transistors 3a and 3b receive the inverted levels of the nodes ND2 and ND1 (/ND2 and /ND1) which are supplied through the buffer part 6, respectively. The input part 4 is composed of nMOS transistors 4a and 4b which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters 1a and 1b. The gates of the nMOS transistors 4a and 4b receive an input signal IN and a reference voltage VREF, respectively. The reference voltage VREF is set at a central voltage between the high-level voltage and low-level voltage of the input signal IN.
The power supply connection part 5 consists of an nMOS transistor 5a which is connected at its drain to the sources of the nMOS transistors 3a, 3b, 4a, and 4b. The nMOS transistor 5a is connected to a ground line VSS at its source, and receives the clock signal CLK at its gate. The buffer part 6 has inverters 6a and 6b for inverting the logic levels of the nodes ND1 and ND2, respectively, and an output circuit 6c. The output circuit 6c has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit 6c is connected to the node /ND1 through an inverter. The gate of the nMOS transistor of the output circuit 6c is connected to the node /ND2.
In the input circuit shown in FIG. 1, when the clock signal CLK is at low level, the pMOS transistors 2a and 2b of the precharging part 2 turn on so that the input nodes ND1 and ND2 of the CMOS inverters 1a and 1b both change to high level. Here, the nMOS transistor 5a is off. While the nodes ND1 and ND2 are at high level, the outputs of the inverters 6a and 6b of the buffer part 6. i.e., the nodes /ND1 and /ND2 are low in level, turning off the nMOS transistors 3a and 3b of the feedback part 3.
Next, the input signal IN is supplied before the clock signal CLK changes to high level. The clock signal CLK of high level turns off the pMOS transistors 2a, 2b of the precharging part 2 and turns on the nMOS transistor 5a of the power supply connection part 5. For example, if the input signal is at high level (a voltage higher than the reference voltage VREF), the source-to-drain resistance of the nMOS transistor 4b becomes lower than that of the nMOS transistor 4a. Consequently, the node ND1 falls below the node ND2 in voltage. The source-to-drain resistance of the pMOS transistor 1a becomes lower than that of the pMOS transistor 1b. As a result, the node ND2 rises in voltage and the node ND1 falls in voltage. That is, the high level of the input signal IN is latched into the latching part 1.
The low level of the node ND1 and the high level of the node ND2 change the nodes /ND1 and /ND2 to high level and low level, respectively. The output circuit 6c of the buffer part 6 receives the low level of the node /ND2 and the inverted level (low level) of the node /ND1, and changes the output signal OUT to high level. That is, the logic level of the input signal IN latched in the latching part 1 is output.
Since the nMOS transistor 3b of the feedback part 3 turns on in response to the high level of the node /ND1, the latching state of the latching part 1 is fixed regardless of the level of the input signal IN. The latching part 1 latches the input signal IN until the clock signal CLK changes to low level.
FIG. 2 shows another example of the input circuit. This input circuit is the input circuit shown in FIG. 1, inverted in polarity. More specifically, the nMOS transistors and pMOS transistors, as well as the power supply line VDD and ground line VSS, are replaced with each other.
The input circuit has a latching part 1, a precharging part 7, a feedback part 8, an input part 9, a power supply connection part 10, and a buffer part 11. The precharging part 7 is composed of two nMOS transistors, 7a and 7b which are connected at their drains to the input nodes ND1 and ND2 of the CMOS inverters 1a and 1b, respectively. The nMOS transistors 7a and 7b are connected to a ground line VSS at their sources, and receive a clock signal /CLK at their gates. The clock signal /CLK is the clock signal CLK inverted in phase.
The feedback part 8 is composed of two pMOS transistors 8a and 8b which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters 1a and 1b. The gates of the pMOS transistors 8a and 8b receive the inverted levels of the nodes ND2 and ND1 (/ND2 and /ND1) which are supplied through the buffer part 11, respectively. The input part 9 is composed of pMOS transistors 9a and 9b which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters 1a and 1b. The gates of the pMOS transistors 9a and 9b receive an input signal IN and a reference voltage VREF, respectively.
The power supply connection part 10 is connected at its drain to the sources of the pMOS transistors 8a, 8b, 9a, and 9b, is connected at its source to a power supply line VDD, and receives the clock signal /CLK at its gate. The buffer part 11 has inverters 11a and 11b for inverting the levels of the nodes ND1 and ND2, respectively, and an output circuit 11c. The output circuit 11c has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit 11c is connected to the node /ND1. The gate of the nMOS transistor of the output circuit 11c is connected to the node /ND2 through an inverter.
In the input circuit shown in FIG. 2, when the clock signal /CLK is at high level, the nMOS transistors 7a and 7b of the precharging part 7 turn on so that the input nodes ND1 and ND2 of the CMOS inverters 1a and 1b both change to low level. Then, the input signal IN is supplied before the clock signal /CLK changes to low level. Then, either one of the nodes ND1 and ND2 changes to high level, and the other to low level. Subsequently, in accordance with the voltages of the nodes ND1 and ND2, either one of the pMOS transistors 8a and 8b of the feedback part 8 turns on so that the latching state is fixed until the clock signal /CLK changes to high level.
In the input circuit shown in FIG. 1, three nMOS transistors (for example, the nMOS transistors 5a, 4a, and the nMOS transistor of the CMOS inverter 1a) are connected in series between the ground line VSS and the nodes ND1, ND2. Similarly, in the input circuit shown in FIG. 2, three pMOS transistors are connected in series between the power supply line VDD and the nodes ND1, ND2. Consequently, when the foregoing input circuits are mounted on semiconductor integrated circuits of lower power supply voltages, it becomes harder for the ground voltage VSS (or the power supply voltage VDD) to be supplied to the latching part 1. This results in a smaller voltage difference between the nodes ND1 and ND2, so that the latching part 1 may latch incorrect data because of slight power supply noise etc.
Additionally, in FIG. 1, the nMOS transistor 4a for receiving the reference voltage VREF is connected to the ground line VSS through the nMOS transistor 5a. Similarly, in FIG. 2, the pMOS transistor 9a for receiving the reference voltage VREF is connected to the power supply line VDD through the pMOS transistor 10a. On this account, the nMOS and pMOS transistors 4a and 9b are more likely to vary in source and drain voltages when the input circuits are in operation. In consequence, if the reference voltage VREF varies due to coupling noise in latching the input signal IN, the input signal IN to be supplied in synchronization with the next clock signal CLK (or /CLK) may not be latched correctly.
It is an object of the present invention to provide a semiconductor integrated circuit having an input circuit capable of receiving an input signal with reliability. In particular, the object is to receive the input signal reliably when the power supply voltage is low.
According to one of the aspects of the semiconductor integrated circuit of the present invention, an input circuit includes a latching part, a power supply connection part, an input part, and a feedback part. In this input circuit, the power supply connection part firstly connects inverting circuits of the input circuit to a first power supply line in response to an activation of a control signal, the first power supply line being supplied with the first power supply voltage. An input switch circuit of the input part connects a second power supply line to one of the input nodes of the inverting circuits through the feedback part in accordance with the input signal, the second power supply line being supplied with the second power supply voltage. Since one of the inverting circuits operates, the latching part is forced into an unbalanced state to latch a logical value corresponding to the input signal. A feedback switch circuit of the feedback part connects only one of the input nodes to the input part in accordance with a level of an output signal output from the latching part. Then, the latching state of the latching part is fixed.
The input part and the feedback part are arranged in series between the second power supply line and the input nodes of the inverting circuits. That is, the input part is connected directly to the input nodes through the latching part. Since a voltage corresponding to the input signal can be supplied to the input nodes directly, a voltage difference between the input nodes of the inverting circuits can be widened quickly in accordance with the input signal. Thus, the input signal can be latched into the latching part with reliability. Since the number of stages of circuits from the input part for receiving the input signal to the latching part can be reduced, the input signal can be latched with reliability even when the power supply voltages are low (even when the difference between the first power supply voltage and the second power supply voltage is small).
According to another aspect of the semiconductor integrated circuit of the present invention, an input circuit includes a latching part, a power supply connection part, an input part, and a feedback part. In this input circuit, the power supply connection part firstly connects inverting circuits of the input circuit to a first power supply line in response to an activation of a control signal, the first power supply line being supplied with the first power supply voltage. An input switch circuit of the input part connects a second power supply line to one of the inverting circuits in accordance with the input signal, the second power supply line being supplied with the second power supply voltage. Since one of the inverting circuits operates, the latching part is forced into an unbalanced state to latch a logical value corresponding to the input signal. A feedback switch circuit of the feedback part connects only one of the input nodes to the second power supply line in accordance with a level of an output signal output from the latching part. Then, the latching state of the latching part is fixed.
The input part and the feedback part are arranged in parallel between the second power supply line and the inverting circuits. That is, the second power supply line is connected directly to the inverting circuits through the input part. Since the second power supply line can be connected directly to the inverting circuits according to the input signal, a voltage difference between the input nodes of the inverting circuits can be widened quickly in accordance with the input signal. Thus, the input signal can be latched into the latching part with reliability. Since the number of stages of circuits from the input part for receiving the input signal to the latching part can be reduced, the input signal can be latched with reliability even when the power supply voltages are low (even when the difference between the first power supply voltage and the second power supply voltage is small).
According to another aspect of the semiconductor integrated circuit of the present invention, a precharging part sets the input nodes of the inverting circuits at a predetermined voltage when the control signal is inactivated. By putting the inverting circuits in an identical state before the latching part operates, the latching part can be quickly rendered out of balance in order to make itself such a state that corresponds to the input signal.
According to another aspect of the semiconductor integrated circuit of the present invention, the output signal is amplified through a buffer part. Supplying the output signal to the feedback part allows a reduction in the time required for determining the latching state of the latching part.
According to another aspect of the semiconductor integrated circuit of the present invention, the input circuit is composed of pMOS transistors and nMOS transistors. The input nodes of the inverting circuits are connected to the second power supply line through two stages-of transistors (pMOS or nMOS transistors of the input part and the feedback part). Consequently, it becomes easier for the second power supply voltage to be transmitted to the input nodes in accordance with the input signal. The input signal can thus be latched with reliability even when the difference between the first power supply voltage and the second power supply voltage is small. As a result, the operation margin can be improved in the case of lower power supply voltages.